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preliminary 1-mbit (64k x 16) static ram cy7c1021dv33 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05460 rev. *c revised january 11, 2005 features ? pin- and function-compatible with cy7c1021cv33 ?high speed ?t aa = 8 ns ? cmos for optimum speed/power ? low active power ?i cc = 75 ma @ 8 ns ? low cmos standby power ?i sb2 = 3 ma ? data retention at 2.0v ? automatic power-down when deselected ? independent control of upper and lower bits ? available in 44-pin tsop ii, 400-mil soj, 48-ball fbga pb-free packages functional description [1] the cy7c1021dv33 is a high-performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power-down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the end of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1021dv33 is available in standard 44-pin tsop type ii 400-mil-wide soj packages, as well as a 48-ball fbga pb-free packages. note: 1. for guidelines on sram system design, please refer to the ?sys tem design guidelines? cypress application note, available on t he internet at www.cypress.com. we logic block diagram pin configuration 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view soj / tsop ii 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc a 4 a 3 oe v ss a 5 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe nc a 1 a 0 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 nc v ss i/o 6 i/o 4 i/o 5 i/o 7 a 6 a 7 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 64k x 16 ram array i/o 1 ?i/o 8 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 512 x 2048 sense amps data in drivers oe a 2 a 1 i/o 9 ?i/o 16 ce we ble bhe a 8
preliminary cy7c1021dv33 document #: 38-05460 rev. *c page 2 of 11 pin configuration selection guide cy7c1021dv33-8 cy7c1021dv33-10 unit maximum access time 810ns maximum operating current 75 60 ma maximum cmos standby current 33ma 48-ball fbga we v cc a 11 a 10 nc a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe nc a 2 a 1 ble v cc i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h (top view) nc nc
preliminary cy7c1021dv33 document #: 38-05460 rev. *c page 3 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [2] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [2] ......................................?0.5v to v cc +0.5v dc input voltage [2] ...................................?0.5v to v cc +0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .... ........... .............. ......>2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 10% industrial ?40 c to +85 c3.3v 10% electrical characteristics over the operating range parameter description test conditions 1021dv33-8 1021dv33-10 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 ? 0.3 0.8 v i ix input load current gnd < v i < v cc ? 1 + 1 ? 1+1 a i oz output leakage current gnd < v i < v cc , output disabled ? 1 + 1 ? 1+1 a i os output short circuit current [3] v cc = max., v out = gnd ?300 ? 300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 75 60 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 10 10 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 33ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8pf c out output capacitance 8 pf thermal resistance [4] parameter description test conditions all - packages unit ja thermal resistance (junction to ambient) [4] still air, soldered on a 3 4.5 inch, two-layer printed circuit board tbd c/w jc thermal resistance (junction to case) [4] tbd c/w notes: 2. v il (min.) = ?2.0v and v ih (max) = v cc + 2v for pulse durations of less than 20 ns. 3. not more than one output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. 4. tested initially and after any design or process changes that may affect these parameters.
preliminary cy7c1021dv33 document #: 38-05460 rev. *c page 4 of 11 ac test loads and waveforms [5] 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 30 pf * capacitive load consists of all components of the test environment (b) r 317 ? r2 351 ? rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5v (c) (a) 3.3v output 5 pf (d) r 317 ? r2 351 ? 8-ns devices: 10 -ns devices: high-z characteristics: output 1.73v equivalent to: th venin equivalent 167 ? switching characteristics over the operating range [6] parameter description 1021dv33-8 1021dv33-10 unit min. max. min. max. read cycle t power [7] v cc (typical) to the first access 100 100 s t rc read cycle time 8 10 ns t aa address to data valid 8 10 ns t oha data hold from address change 3 3 ns t ace ce low to data valid 8 10 ns t doe oe low to data valid 5 5 ns t lzoe oe low to low-z [8] 00ns t hzoe oe high to high-z [8, 9] 45ns t lzce ce low to low-z [8] 33ns t hzce ce high to high-z [8, 9] 45ns t pu [10] ce low to power-up 0 0 ns t pd [10] ce high to power-down 8 10 ns t dbe byte enable to data valid 5 5 ns t lzbe byte enable to low-z 0 0 ns t hzbe byte disable to high-z 4 5 ns write cycle [11] t wc write cycle time 8 10 ns t sce ce low to write end 7 8 ns t aw address set-up to write end 7 8 ns notes: 5. ac characteristics (except high-z) for all 8-ns parts are test ed using the load conditions shown in figure (a). all other spe eds are tested using the thevenin load shown in figure (b). high-z characteristics are tested for all speeds using the test load shown in figure (d). 6. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. 7. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in (d) of ac test loads. transition is measured 200 mv from steady-state vol tage. 10. this parameter is guaranteed by design and is not tested. 11. the internal write time of the memory is defined by the overlap of ce low, we low and bhe /ble low. ce , we and bhe /ble must be low to initiate a write, and the transition of these signals can terminate the write. t he input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
preliminary cy7c1021dv33 document #: 38-05460 rev. *c page 5 of 11 t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 6 7 ns t sd data set-up to write end 5 5 ns t hd data hold from write end 0 0 ns t lzwe we high to low-z [8] 33ns t hzwe we low to high-z [8, 9] 45ns t bw byte enable to end of write 6 7 ns switching characteristics over the operating range [6] parameter description 1021dv33-8 1021dv33-10 unit min. max. min. max. data retention characteristics over the operating range parameter description conditions min. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current non-l, com?l / ind?l v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 3ma l-version only 1.2 ma t cdr [4] chip deselect to data retention time 0 ns t r [12] operation recovery time t rc ns data retention waveform switching waveforms read cycle no. 1 [13, 14] notes: 12. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 s or stable at v cc(min.) > 50 s. 13. device is continuously selected. oe , ce , bhe and/or bhe = v il . 14. we is high for read cycle. 4.5v 4.5v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out
preliminary cy7c1021dv33 document #: 38-05460 rev. *c page 6 of 11 read cycle no. 2 (oe controlled) [14, 15] write cycle no. 1 (ce controlled) [16, 17] notes: 15. address valid prior to or coincident with ce transition low. 16. data i/o is high impedance if oe or bhe and/or ble = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe, ble t
preliminary cy7c1021dv33 document #: 38-05460 rev. *c page 7 of 11 write cycle no. 2 (ble or bhe controlled) write cycle no. 3 (we controlled, low) switching waveforms (continued) t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe
preliminary cy7c1021dv33 document #: 38-05460 rev. *c page 8 of 11 truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high-z high-z power-down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high-z read ? lower bits only active (i cc ) h l high-z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high-z write ? lower bits only active (i cc ) h l high-z data in write ? upper bits only active (i cc ) l h h x x high-z high-z selected, outputs disabled active (i cc ) l x x h h high-z high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 8 cy7c1021dv33-8vxc v34 44-lead (400-mil) molded soj (pb-free) commercial cy7c1021dv33-8vxi industrial cy7c1021dv33-8zxc z44 44-lead tsop type ii (pb-free) commercial cy7c1021dv33-8zxi industrial cy7c1021dv33-8baxc ba48a 48-ball fbga (pb-free) commercial cy7c1021dv33-8baxi industrial 10 cy7c1021dv33-10vxc v34 44-lead (400-mil) molded soj (pb-free) commercial cy7c1021dv33-10vxi industrial CY7C1021DV33-10ZXC z44 44-lead tsop type ii (pb-free) commercial cy7c1021dv33-10zxi industrial cy7c1021dv33-10baxc ba48a 48-ball fbga (pb-free) commercial cy7c1021dv33-10baxi industrial shaded areas contain advance information. plea se contact your local cypress sales repr esentative for availability of these part s.
preliminary cy7c1021dv33 document #: 38-05460 rev. *c page 9 of 11 package diagrams 48-ball (7.00 mm x 7.00 mm x 1.2 mm) fbga ba48a 51-85096-*e 44-lead (400-mil) molded soj v34 51-85082-*b
preliminary cy7c1021dv33 document #: 38-05460 rev. *c page 10 of 11 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this doc ument are the trademarks of their respective holders. package diagrams (continued) 44-pin tsop ii z44 51-85087-*a
preliminary cy7c1021dv33 document #: 38-05460 rev. *c page 11 of 11 document history page document title: cy7c1021dv33 1-mbit (64k x 16) static ram (preliminary) document number: 38-05460 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance information data sheet for c9 ipp *a 233693 see ecn rkf dc parameters are modified as per eros (spec # 01-02165). pb-free offering in ordering information *b 263769 see ecn rkf changed i/o 1 ? i/o 16 to i/o 0 ? i/o 15 added data retention characteristics table added t power spec in switching characteristics table shaded ordering information *c 307601 see ecn rkf reduced speed bins to -8 and -10 ns

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